1. Technical Field
The present invention described herein relates to a semiconductor integrated circuit, and more particularly, to a circuit for changing a frequency of a signal and a frequency change method thereof.
2. Related Art
A semiconductor integrated circuit needs a clock signal having a frequency higher than a frequency of a clock signal provided from an external controller in order to test the operation thereof.
A semiconductor test device does not provide a suitable clock signal having a high frequency for testing the semiconductor integrated circuit.
Therefore, a signal frequency change circuit, which changes a frequency of a clock signal provided from the outside, for example, to a frequency twice as high, is provided internally within the semiconductor integrated circuit.
FIG. 1 is a circuit diagram of a signal frequency change circuit 1 according to one example well known in the prior art and FIG. 2 is a block diagram of a signal frequency change circuit 10 according to another example well known in the prior art.
As shown in FIG. 1, the signal frequency change circuit 1 according to the prior art includes a delay device ‘DLY’ and an XOR gate ‘XOR1’.
The signal frequency change circuit 1 shown in FIG. 1 performs XOR on a clock signal ‘CLK’ and an output signal ‘A’ of the delay device ‘DLY’ to generate an output signal ‘OUT’ having a frequency that is two times higher than a frequency of the clock signal ‘CLK’.
As shown in FIG. 2, the signal frequency change circuit 10 according to another embodiment of the prior art includes a counter 11, an oscillator 12, and a logic circuit 13.
In the signal frequency change circuit 10 shown in FIG. 2, the oscillator 12 generates an oscillation signal (OSC) having a higher frequency than the clock signal ‘CLK’ and the counter 11 counts and outputs the oscillation signal ‘OSC’. And, the logic circuit 13 generates the output signal ‘OUT’ having a period corresponding to half of one period of the clock signal ‘CLK’, that is, a frequency that is two times higher than the frequency of the clock signal ‘CLK’ using the output of the counter 11.
Even though a structure of the signal frequency change circuit 1 according to the prior art is simple, problems can arise in that a duty cycle of the output signal ‘OUT’ significantly fluctuates according to the delay device ‘DLY’, which increases the probability of generating a duty cycle error. For example, the duty error of the clock signal ‘CLK’ can occur as jitter in a rising edge of the output signal ‘OUT’.
Further, the signal frequency change circuit 10 according to the prior art can exhibit problems in that the current consumption is increased according to the operation of the oscillator 12 and the circuit area is increased according to the increase in the number of bits of the output signal of the counter 11.